When #TXE is Low, data intake to FT device. And data does not intake when #TXE is High. But FT device clock is always generating.
Then We have to prevent clock to not work Counter(or FIFO) using CONTROL block between #TXE is High.
But the timing relation between #TXE and CLK as below,
The timing in #TXE became Low, CLKout signal has short pulse, and the counter(FIFO) increment one step. And one data can not read.
Therfore one data was lost ( Remark in this mode, FT232H or FT2232H pick-up data at rising edge of CLKin).
Then CONTROL Block change as below,
Counter(FIFO) control signal changes as below,
we can get lossless data.